Hierarchical strategies for efficient fault recovery on the reconfigurable PAnDA device

A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA. Two fault recovery techniques, stochastic and deterministic strategies, are proposed and results of each, as well as a comparison of the two, are presented. Both approaches are based on creating algorithms performing fine-grained hierarchical partial reconfiguration on faulty circuits in order to repair them. While the stochastic approach provides insights into feasibility of the method, the deterministic approach aims to generate optimal repair strategies for generic faults induced into a specific circuit. It is shown that both techniques successfully repair the benchmark circuits used after random faults are induced in random circuit locations, and the deterministic strategies are shown to operate efficiently and effectively after optimisation for a specific use case. The methods are shown to be generally applicable to any circuit on PAnDA, and to be straightforwardly customisable for any FPGA fabric providing some regularity and symmetry in its structure

Multi-objective Optimisation of Digital Circuits based on Cell Mapping in an Industrial EDA Flow

Modern electronic design automation (EDA) tools can handle the complexity of state-of-the-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independent-optimised design step, overhead and inefficiency can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space, but has the potential to provide solutions with improved performance. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, preceding physical implementation, through multi-objective population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block-level, where it is capable of expanding the design space and offers a set of trade-off solutions for different case-specific utilisation. We have applied the proposed MOEDA framework to ISCAS-85 and EPFL benchmark circuits using a commercial 65nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow, and how simultaneously a significant improvement in PPA metrics is achieved

Jography: Exploring meanings, experiences and spatialities of recreational road-running

Jogging is a relatively under-researched mobile practice with much existing literature focusing on ‘serious’ and competitive running. In this paper, we provide an account of some of the movements, meanings and experiences that together help produce the practice of jogging in the south-western English city of Plymouth. Drawing upon participant diaries and interviews, we uncover rich detail about how joggers ascribe not one but a number of meanings to their practice. Some of these are positive, some are negative; some complement each other and some compete with each other. We also consider how the experiences of joggers can be shaped by their ongoing need to develop tactics capable of enabling them to negotiate space with non-joggers. This is in some contrast to more competitive running that occurs in the separated space of an athletics track. Our sense is that better awareness of the meanings and experiences of jogging will be of value if the advertised health and sustainability benefits of the practice are to be more effectively encouraged and promoted

A Multi-objective Evolutionary Approach for Efficient Kernel Size and Shape for CNN

While state-of-the-art development in CNN topology, such as VGGNet and ResNet, have become increasingly accurate, these networks are computationally expensive involving billions of arithmetic operations and parameters. To improve the classification accuracy, state-of-the-art CNNs usually involve large and complex convolutional layers. However, for certain applications, e.g. Internet of Things (IoT), where such CNNs are to be implemented on resource-constrained platforms, the CNN architectures have to be small and efficient. To deal with this problem, reducing the resource consumption in convolutional layers has become one of the most significant solutions. In this work, a multi-objective optimisation approach is proposed to trade-off between the amount of computation and network accuracy by using Multi-Objective Evolutionary Algorithms (MOEAs). The number of convolution kernels and the size of these kernels are proportional to computational resource consumption of CNNs. Therefore, this paper considers optimising the computational resource consumption by reducing the size and number of kernels in convolutional layers. Additionally, the use of unconventional kernel shapes has been investigated and results show these clearly outperform the commonly used square convolution kernels. The main contributions of this paper are therefore a methodology to significantly reduce computational cost of CNNs, based on unconventional kernel shapes, and provide different trade-offs for specific use cases. The experimental results further demonstrate that the proposed method achieves large improvements in resource consumption with no significant reduction in network performance. Compared with the benchmark CNN, the best trade-off architecture shows a reduction in multiplications of up to 6X and with slight increase in classification accuracy on CIFAR-10 dataset.Comment: 13 pages paper, plus 17 papers supplementary material

Predicting Shielding Effectiveness of Populated Enclosures Using Absorption Cross Section of PCBs

Shielding effectiveness (SE) is an important measure of how well an enclosure reduces the electromagnetic (EM) field incident upon it. Commonly, when the shielding effectiveness of an enclosure is stated it is for the case when the enclosure is empty. Including contents such as printed circuit boards (PCBs) in the enclosure will affect the shielding effectiveness as the PCB absorbs EM energy. One technique of determining how much energy a PCB absorbs is to measure its absorption cross section (ACS) using a reverberation chamber (RC). The measured ACS can be used to predict the shielding effectiveness of an enclosure when the PCB is inside it using power balance techniques. In this paper the ACS of a number of PCBs are measured both individually and in closely stacked groups. This information is then used to show how the ACS can be used to calculate shielding effectiveness and the results are compared to direct measurement of the SE of the enclosure containing a PCB. Knowledge of the ACS of typical or particular PCBs could be used by engineers to estimate the real shielding effectiveness of an enclosure with contents, when designing electronic systems

Penning-trap Q-value determination of the Ga-71(v, e(-))Ge-71 reaction using threshold charge breeding of on-line produced isotopes

<p>We present a first direct Q-value measurement of the Ga-71(v, e(-))Ge-71 reaction using the TITAN mass-measurement facility at ISAC/TRIUMF. The measurements were performed in a Penning trap on neon-like Ga-71(21+) and Ge-71(22+) using isobar separation of the on-line produced mother and daughter nuclei through threshold charge breeding in an electron-beam ion trap. In addition, isoionic samples of Ga-71(21+) and Ge-71(21+) were stored concurrently in the Penning trap and provided a separate Q-value measurement. Both independent measurements result in a combined Q-value of 233.5 +/- 1.2 keV, which is in agreement with the previously accepted Q-value for the v cross-section calculations. Together with a recent measurement of the v-response from the excited states in Ge-71, we conclude that there are no further uncertainties in the nuclear structure, which could remove the persistent discrepancy between the SAGE and GALLEX calibration measurements performed with neutrinos from reactor-produced Cr-51 and Ar-37 sources and the theoretical expectation. (c) 2013 Elsevier B.V. All rights reserved.</p>

A Novel Multi-objective Optimisation Algorithm for Routability and Timing Driven Circuit Clustering on FPGAs

Circuit clustering algorithms fit synthesised circuits into FPGA configurable logic blocks (CLBs) efficiently. This fundamental process in FPGA CAD flow directly impacts both effort required and performance achievable in subsequent place-and-route processes. Circuit clustering is limited by hardware constraints of specific target architectures. Hence, better circuit clustering approaches are essential for improving device utilisation whilst at the same time optimising circuit performance parameters such as, e.g., power and delay. In this paper, we present a method based on multi-objective genetic algorithm (MOGA) to facilitate circuit clustering. We address a number of challenges including CLB input bandwidth constraints, improvement of CLB utilisation, minimisation of interconnects between CLBs. Our new approach has been validated using the "Golden 20" MCNC benchmark circuits that are regularly used in FPGA-related literature. The results show that the method proposed in this paper achieves improvements of up to 50% in clustering, routability and timing when compared to state-of-the-art approaches including VPack, T-VPack, RPack, DPack, HDPack, MOPack and iRAC. Key contribution of this work is a flexible EDA flow that can incorporate numerous objectives required to successfully tackle real-world circuit design on FPGA, providing device utilisation at increased design performance

Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs

A national-scale assessment of climate change impacts on species: assessing the balance of risks and opportunities for multiple taxa

It is important for conservationists to be able to assess the risks that climate change poses to species, in order to inform decision making. Using standardised and repeatable methods, we present a national-scale assessment of the risks of range loss and opportunities for range expansion, that climate change could pose for over 3,000 plants and animals that occur in England. A basic risk assessment that compared projected future changes in potential range with recently observed changes classified 21% of species as being at high risk and 6% at medium risk of range loss under a B1 climate change scenario. A greater number of species were classified as having a medium (16%) or high (38%) opportunity to potentially expand their distribution. A more comprehensive assessment, incorporating additional ecological information, including potentially confounding and exacerbating factors, was applied to 402 species, of which 35 % were at risk of range loss and 42 % may expand their range extent. This study covers a temperate region with a significant proportion of species at their poleward range limit. The balance of risks and opportunities from climate change may be different elsewhere. The outcome of both risk assessments varied between taxonomic groups, with bryophytes and vascular plants containing the greatest proportion of species at risk from climate change. Upland habitats contained more species at risk than other habitats. Whilst the overall pattern was clear, confidence was generally low for individual assessments, with the exception of well-studied taxa such as birds. In response to climate change, nature conservation needs to plan for changing species distributions and increasing uncertainty of the future